Signal amplifier system



July 26, 1960 R. H. BETER ETAL 2,946,957

SIGNAL AMPLIFIER SYSTEM Filed March 10, 1955 fraggvgy SIGNAL AMPLIFIER SYSTEM Ralph H. Beter, Philadelphia, and Morris Rubinoff, Sharon Hill, Pa., assignors to Philco Corporation, Philadelphia, Pa., a corporation of Pennsylvania Filed Mar. 1t), 1955, Ser. No. 493,366

6 Claims. (Cl. S28-53) pulsel series. Circuits of the iirst classV rare generallyknown vas lamplifiers and those of the second classY are Coincidence circuits or. gate circuits or buifercircuits yaccount for a large portion.

generally known as inverters.

of the thirdclass of circuits. lt will be recognized that all three forms of circuits are also found in electronic devices other than digital computers. In all of the types of circuits mentioned above, one of the basic elements around which the circuits are built is thevacuum tube amplifier stage. lt is conventional practice to supply the pulses to be` amplified or combined to one or more grids of one or more vacuum tubes which have the anodes` thereof returned to a source of direct potential through a lo-ad impedance foreach tube. In many instances the pulse signals drive the amplifiers into heavy conduction thus placing a heavy load on the source of anode supply potential. Decoupling networks are often required to prevent signals supplied to one amplifier stage from adversely affecting the operation of other amplifier stages. v Y

As suggested above, the combination of two or more pulses or pulse series is usually accomplished in va gate circuit or coincidence circuit. One common form of coincidence circuit employs an amplifier tube having two or more signal grids.

Therefore it is an object of the present inventionto provide a novel ampliiier circuit which does not require the use of decoupling filters in the power supply leads.

It is a further object of the present invention to pro` vide a novel circuit in which Vthe number of input leads is flessithan the number required for conventional circuits. I

vStill another object of the invention is to provide a novel circuit requiring lfewer control elements. g I

' A further object of the invention is to provide a novel One series of pulses is supplied to one cont-rol grid and the second series of pulsestransistor circuit which is the equivalent of a circuit employing a multigrid vacuum tube.

Another object of the invention is to provide a novel transistorized gate circuit which is capable of providing results not heretofore obtainable in circuits employing a single active element.

In general these and other objects of the invention are achieved by employing a pulse type power supply in place of the usual source of direct potential or, alternatively, of employing one of the signals to be processed as the anode supply of the amplifier stage while impress? ing another signal on-V a control element in the usual manner. during inactive periods of the ampliiier stage.

For a better understanding of the invention together with other and further objects thereof reference should now be made to the following detailed description which is to be read in conjunction with the accompanying drawings in which:

Fig. l isa diagram, partially in block form, of one preferred embodiment of the invention;

Fig. 2 is a series of waveforms which illustrate the operation of the system of Fig. l and Fig. 3 is a schematic diagram `of a second preferred embodiment of the invention.

In Fig. 1 a triode vacuum tube 10 is supplied with anode potential from clocking pulse source 12. Thisv connection is made through an anode load impedance 14. A lead 1S is shown in Fig. l to illustrate that the pulses supplied to tube 10 may serve also as the sourceA of anode supply potential for other amplifier stages.

The signals to be amplified are supplied to the con-V trol, grid of tube 10 from signal pulse generator 20 by wayof the resistor-capacitor coupling network 22. A

negative bias source, schematically represented by thev minus sign in Figure l, is provided for `biasing the grid of tube 10 below cut off potential. Generator 20 of Fig. l may be any one oft-he various Ysources of signals which require ampliiication. ln'one instance it may be a large section of a digital lcomputer including several hundred Ycomponents while in another instance it maycomprise a simple encoder circuit or 4a gated put of signal pulse generator 2@ which do occur in time.

coincidence withthe signals supplied by clocking pulse sourcev 12. It should be noted that theV use of the clocking' pulses as the anode supply pulses reduces by one -the' number of inputs required in the coincidence amplifier stage. Signals may be supplied topulse generator 20 by way of lead 25 to control the nature ofthe output signal of generator 20. This control maytake the form of suppressing pulses which would normallyappear. in theoutput of generator 2t) -in-the absence lof such control.

YThe signal appearing at the anode of tube 1t? is supplied` to the control grid of a second ampliiierstage through a delay network 26. For reasons which will appear presently, delay network 26 should have a delay equal to an` integral multiple, including the first, of the repetition period of source 12. In other embodimentsof the invention capacitors, multivibrators or other delay or storage elements may be employed to store or maintain the signal until the signal is no longer needed by the following stage. Furthermore additional gating operations may be per- Patented July 26, 196thv Means are provided for storing output signals seamen? formed in' the" coupling network connecting tube 10 to tube' 28; through additional circuits"associated^ with" thecontrol grid of tube 28 or through circuits associated with additional control grids of. tube 28. The manner in which' su'ch gating operations can be' performed" iswell within the ,knowledge of the4 workeriir^` thc-computerP art' and", for this reason', we'havewho'sen" to" illustrate? the inventioninits simplest'form.' l

second'amplier stage isrepresentediinF-igij lb'yia' triode vacuum tube 28 havinga loa'd impcdaricecon'- nectin'g its anode'to `a secondlead32 from p uls'e source 125 The grid' of tube* ZS` isfbiased"l atapProXimately cutL oifipotential by ythe source schematically' represented: by'- tlieflegend' BIAS Thefoperationof 'the systerrr of' Fig. ljwill ncw'berexL' plained withreferencetdFigiZ. Ii'rFig: 2waveform A" representsthepulse signals supplied bysourcerlZito'th'e' amplifier stage including; tube'10." The"pu'lses"supplie'd" byjsource 1'2' are of suicientamplitude'to' supply the nor.- rnal` anodeA potential to tubel: Withsome" types' 'ofsubminiature'tubes now' used' in' digital -`computers' the arnpli tude'offthe-pulses may be oftheorder of 28"'volts:

Waveform B in Fig. 2 represents the signals appearing" at'tlie-'output of 'generator 20. It 'has'been assumed* arbitrarily that a pulse'signal appears'irr the'output'of 'gen1- erator'20`for' each of the' first; third, and' fourth` pulses supplied byl source 12 but that'noxpnlsejappears'atthe' outpntlof 'generator 20 in' time' coincidence', with thesecnd pulse from source 12. As'shown'in'Fig'.' Ztliepulses' suppliedibysource 12 are offgreaterduraton' than the signals supplied' by generator 20.'

VVavefori-n` C represents 'theY signal' appearingjat' the' anodef of tube 10. Note that for' p ulses 1,- 3 andf4 ofy waveform' A, the potentialy at'the an'o'de' ofitube-l'rst' rises as'the pulse lis supplied' by source 12; thenfallsms the-grid'of'tube 10 becomes'positive'in response'to` the pulseesupplied'by generator20, `again goes'positivepas the' pulsefi'om generator 20 terminates; and' iinally'falls to its"original value at the termination` of' the'v pulse f 'r'o'rn' source 12.

Waveform D represents the signal at'the'grid" of `tubeg 28;" Waveform D is the sameas wavefornLC' except' that it is delayed in time by"aninterval'd"as'a'result'of itsipassage through delay 'line' 261 Waveforms'El, E2 and E3 represent'the signals`"appear' ing-at the anode of tube 28 for' three different' sets.' of' conditions; Waveform El represents' the; signal at' the; anode'ifthe anode supply' pulses'to tube' 28la're' ofthe, same durations as the anode'supply pulses supplied'to' tube 'and if the delay d'is'exactly'equal to'therepetition-period of waveform A. A small plateau is generallyI present even though the grid of tube 28'ishighly'positive. Apositivepulseappears wheneverQa negativepulse ap, pearsl inwaveform Dl The p ulsesmay 'be 'separated'fro'm'V the plateau by proper selection of'tbias'p'otentials in thestage/ following tube 10.

Waveform E2 represents an'. undesirable condition which may exist if for'some'reason the delay of'the delay network 26' is other than an integral multiple of the period ofthe'signals from source'12.r If the'delay 'isgreatenthan this period; for example'the delay d of Fig. E2', the.anodeV o'tube 28'will first rise'with' the application ofthe` anode pulse` from source'12 and then*v fall. as the positive pulse is-supplied. to'the control grid' from delay network 26.-

Wvefrm E3 illustrates'that'the above-mentioneddii# culty may be avoided by narrowngthe anode Isupply pulse'supplied to tube 28` to the interval -'limitedfby the. broken 'lines' 36. in` waveform A. This 'insures that ,thel positivet signal is'suppliedito.' the gridrof'tube Z8`befre the'anode'pulseis' applied.. TleLplateauwhich remains iii-the signal shownzin waveform B3' maybeeli'minatd" byproper choice' of "bias in the stage. fllwing tnbe 282 Ifsliould be noted th'at'itis only necessary for. source..12.. toisupply anode-supp ly, pulses of 'two fwidths. f. The widen pulses'are supplied to' stages havingpositive sig'nalsrsup: 75

it plied to the control grid and the narrower pulses are suppiiedto'the'intermediate stages.

In illustrating the operation of the system df Fig. 1 it has been assumed that the shape of the pulses is preserved in the coupling networks. This is not necessary in all applications of the present invention. In some instances it may be desirable'toemploy coupling networks which dilerentiate the pulse signals inorder to provide Y precise controlo'f'iblockn'g oscillators; triggered multivibratorslortheliker In otherzembod-imentswf the: inverttionithef delay or.'storage circuits: between the: amplifiers may .bei arranged tot broaden each;pulse passing'.'thcre through to insure .that.a signalpulse receivedby an amplier will be present for the full duration of the clock pulse. In a circuinarrangedlin. this'manner the clock pulse determines the time of occurrence of the leading and trailing edges of the output pulse. Timing pulse source 12 maysupply pulses to other circuits in the intervals" between' the pulses' shown in' waveform: A. Obviously there can be'no' interference: between these other circuitsand'the'circuitssupplied by' the pulsesof' waveform Aisince' tlie various'sets of circuits'are active.

number'ofcircuit'components required. Fig.. 1" shows` onlyav single clocking' pulse" source' and' a single' source ofpulses' to" be processed'. It is within the scope' of '.the'

inventionto' apply 'pulses' from several sources'.to one or' more' control'grids or'elements'and. so arrange thezcir cuit'th'at an output'signal is'present' for any preselected.' combination'ofsignalpulses and clocking'pulses.

Fig 3'n illustrates" a' transistor circuit embodying the principles' of' the present'inventionY which iscapable of' performing, functions' which.cannot be' duplicated in a'.

single' vacuum' tube. ampliti'er'stage.' In Fig.. 3 an' NPN transistor'v 50i` is' arrangedA so that' the emitter 51l is' grounded? The'bas'e Siis'connected to' one source 52`of" pulse'signals' The collector 55"`isj connected to a second" Y source 54 of'pulse'signals through'a load"resisto'156.` A'

lead 5K8 from the collector 55 is provided asja'means for drivingia signal. from thelcir'cuit.` Again pulse' sources SZand' 54 may' comprise whole. sectionslof a computer or they'may,'be'.basic'pulse generatingA circuits. These pulse'sources maysupplypulsesat regular or irregular intervalab'ut atleast s'ome of these pulses from one of the'sourcesv must'occur in time coincidence withpulses fromthe 'other source.

The'cicu'it ofFig. 3 operates in the followingt manner. The pulses-'suppldfrom source 52' to the base'53' are positive and of'suicient amplitude to cause transistor 50fto'app'ear as'a short circuitffrom emitter S1 to' co1` lectorjSS-l` 'Ilierefore'foutputlead 58"will remain'sub; stantially' at'gr'oundpotential for 'the'duratio'n of the'puls'es' supplied* by; source-52 regardless' of 'the' signal 'supplied by source 54'. In other words, a positive pulse supplied by@ source; 54 will-'appear at' output lead' 58' only in" the off'Fig. Z'thus acts' as 'an inhibit'gate in'which one positivepulserinhibits .'orblocks '.a-z positive'pulsefr'om another source. Inhibit:A gatefcircuits; are widely used'in com'- puter `circuitssto'.- providerl Boolean: (logical.) inversion: of.

the function of pulses. The reason that the transistory circuitofeFig; 31 isf-superior to. known '.forms lof-.vaeuum tube circuits vis-:that` thef plateaufoundlin the .waveformsn of.. Eig, .3.Y are. almostrcompletelyl absent from -the output t lead 58 owing to the very low impedance between emitter and collector when the base is supplied with a large positive pulse. A somewhat similar result can be achieved in a multigrid vacuum tube coincidence circuit but such a circuit will only operate on positive pulses and the polarity of the output pulses is the reverse of the polarity of the input pulses.V f

The circuit of Fig. 3 may be modified to operate with negative pulses by substituting a PNP type transistor for the NPN type shown in Fig.r 3. Point contact, junction or Vsurface barrier transistors may be employed in the circuit of Fig. 3.

While there have been described what are at present considered to be the preferred embodiments ofthe invention it will be apparent that various modifications and other embodiments will occur to those skilled in the art within the scope ofthe invention. Accordingly we desire the scope of our invention to be limited only by the appended claims.

What is claimed is:

l. A system for processing signals, said system comprising first and second variable impedance elements each having first and secondterminals and a control ele'- ment, the impedance between said first and second terminals of each of said variable impedance elements being afun'ction of the potentialVV of said control element with respect to one of said terminals, a first load impedance having first and second terminals, said second terminal of said first load impedance being connected to said second terminal of said first vaniable impedance element, means for supplying said signals to be processed to said control element of said first impedance element so as to vary the potential thereof with respect to said one terminal, a second source of constant amplitude pulses, said second source having first and second terminals and being arranged so that one of the pulses supplied thereby occurs in time coincidence with each of said signals to be proces-sed, the duration of each of said pulses from said second source being at least equal to approximately the duration of the pulse to be processed which occurs in time coincidence therewith, the first and second terminals of said second source being connected, respectively, to said first terminal of said rst load impedance and said first terminal of said rst variable impedance element, a second load impedance having first and second terminals, said second terminal of said second load impedance being connected to said second terminal lof said second variable impedance element, a third source of constant amplitude pulses, said third source providing a series of pulses in which selected pulses are spaced by a fixed time delay from pulses of said second source occurring in time coincidence with said signals to be processed, said third source of pulses being connected between said first terminal of said second load impedance and said `first terminal of said second variable impedance element, signal delay means having a time delay equal to said fixed time delay, said signal delay means being connected from said second terminal of said first variable impedance element to said control element of said second variable impedance element, and means associated with said second terminal of said second variable impedance element for extracting asignal from said system.

2. A system for amplifying pulses, said system comprising first and second vacuum tubes, each having a cathode, an anode, and a control grid, the cathode of each of said tubes being connected to a point of fixed reference potential, first and second load impedances connected, respectively, to the anodes of said first and second vacuum tubes, a first source of periodic, constant amplitude anode supply pulses connected to said first load impedance, a second source of periodic, constant amplitude anode supply pulses connected to said second load impedance, the duration of each of the pulses provided by said lirst and second sources being at least equal to approximately the duration of the pulses to be amplified, a delay network connected from the anode of said first vacuum tube to the control grid of said second vacuum tube, said delay network having a delay equal to the delay between the occurrence of a selected pulse from said first source and a selected pulse Vfrom said second source, means for supplying the pulses to be amplified to the control grid of said first vacuum tubeV and means associated with the anode of said second vacuum tube for extracting a signal from said system.

3. A system for processing signals comprising a first variable impedance means and a first load impedance connected in a rst series circuit, a second Variable impedance means and a second load impedance connected in a second series circuit, each of said variable impedance means being provided with a control element, the impedance of each of said variable impedance means being a function of the potential of said control element with respect to a second point on said variable impedance means, means for supplying said pulses to be processed to said control element of said first variable impedance means so as to vary the potential thereof with respect to said second point on said first variable impedance means, a f irst source of constant amplitude pulses connected across said first series circuit, said first source being so arranged that one of the pulses supplied thereby occurs in time coincidence with each of said pulses to be processed, the duration of each of the pulses from said first source being at least equal to approximately the duration of the pulse to be processed which occurs in time coincidence therewith, a second source of constant amplitude pulses connected across said second series circuit, said second source being arranged to provide aseries of pulses in which selected pulses are spaced by a xed time delay from pulses of said first source occurring in time coincidence with said pulses to be processed, signal delay means connecting said first series circuit to said control element of said second variable impedance means, said signal delay means being so connected that the potential of said control element of said second variable impedance means is influenced by the signal appearing across the load impedance of said first series circuit, said signal delay means having a time delay equal to said fixed time delay, and means associated with said second load impedance for extracting a signal from said system.

4. A system for processing pulses comprising first rand second normally inactive signal processing stages, means for rendering said first signal processing stage active during time intervals of limited duration, said active intervals recurring periodically at a given repetition rate, means for rendering said second signal processing stage active during time intervals of limited duration, said last-mentioned time intervals recurring at the same repetition rate as said first-mentioned time intervals, delay means coupling the output of said first signal processing stage to the inputof said second signal processing stage, said delay means having a delay time substantially equal to the time spacing between a selected active time interval of said first stage and a non-coincident active time interval of said second stage, means for supplying a signal to be processed to the input of said rst signal processing stage and means for deriving an output signal from the output of said second signal processing stage.

5. A system for processing signals comprising at least three series circuits arranged in cascade, each of said series circuits comprising a variable impedance means and a load impedance connected in series therewith, each of said variable impedance means being provided with a control element, the impedance of each of said variable impedance means being a function of the potential of said control element with respect to a second point on said variable impedance means, a first source of constant amplitude pulses connected across the first and each additional odd-nlnnbered series circuit in said cascade arrangement, said first source being so arranged that one ofzthe pulsesisnppliedtherebyoccursfintmefcoincidence '-eachffnffthefpulses to" lbeuprocessed; the` duration of "eachfoflthe pulses :ffrornlsa'id llrst'source being -at least equal to approximatelythefduration offthezpulses vto'be processed which :foceur :in rtimelcoincidence ltherewith, va

secondfisource'foffr'constant amplitudefpuls'es vconnected -across thefse'cond seniescircuit'f and'fea'ch additional-evennnnber'ed-seri'esicircuit;if any, iinllsaid cascadef'arrangem'e'nt said second "isource being arranged fto-pro1ide a series/:ofipulsesiin which select'edl-ipnlsesf-aref'spacd:-by a occur initimercoincid'ence Awithsaidvpulses to be processed, .fa'rst I= series `-0l? signal =delay means, leach "delay fmeansof2 said` '-rst s'eriesconnecting@al corresponding oddmumbered serieswcircuitito`\saidfcontrolfelement of the `yaiia-ble impe'dancemeans in theffollowing-even-numbered variable-'impedance'means in the Yfollowing odd-numbered series circuit; said`sign'al .'delay means of saidfsecond series being so connected vthat Athe vpotential oflsaid control element ofIsad5 variable impedancefmeansfof "the fllowing stagevis' influenced lbyY thesgnalffappeaningf'across the load impedance 'of' the preceding"stage,=saidasignal delay means Lof 'saidV `second seri'esffeach having =a ftime'delay equal to 'the difference between' the time;` delayesyffsaid delay. means offsaidv vfirst iseries' landanintegr'alilluminer of periods of said pulses from said irstsource' o'f constant amplitudetpulses, means for 'supplying saidzpuisesi to'be processed tothe control Y-element of the variable -'impedance means ofthe rst 'series circuit :sor'asitowary the potential thereof with respect :toxsaid second zzpointton that variable impedance means, and :means associated with a load impedance 'of' one Aof,` said.series'fcircuitsfor extracting an output. signal from'isaidv'system.

6. A system for .processingfsignals `las delined Ibyiclaiin 5 wherein constant 4Vamplitudepulsesfsnplblied :byfsaid second source Vare Yofi'shorterr-'dnration :than -the :pulses supplied'by said rst source. 

